Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion

ABSTRACT

A gate wire is formed on a substrate. Next, after forming a gate insulating film, a semiconductor layer and an ohmic contact layer subsequently are formed thereon. Next, a data wire is formed. Next, a passivation layer and an organic insulating film are deposited, and patterned to form contact holes for exposing the drain electrode, the gate pad and the data pad respectively. Here, the organic insulating film around the contact holes is formed thinner than that in the other portions. Next, the organic insulating film around the contact holes is removed by an ashing process to expose the borderline of the passivation layer in the contact holes, thereby removing an under-cut. Then, a pixel electrode, an assistant gate pad and an assistant data pad respectively connected to the drain electrode, the gate pad and the data pad are formed.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention

[0002] The present invention relates to a contact portion ofsemiconductor device and a method for manufacturing the same, and a thinfilm transistor array panel for display device including the contactportion and the method for manufacturing the same.

[0003] (b) Description of the Related Art

[0004] In general, it is preferable that, as a semiconductor device ismore integrated, an area of the device is optimized and a wiring thereofis made of multi-layers. In this case, preferably, an interlayerinsulating film is made of material with a low dielectric constant inorder to minimize an interference of signals transferred through thewiring, and the wiring transferring the same signals has to be connectedelectrically by forming a contact hole in an insulating film. However,if an under-cut is generated on the contact portion on forming thecontact hole by etching the insulating film, a step coverage of thecontact portion becomes bad. This causes a problem that a profile of thewiring formed on the insulating film becomes bad or the wiring in thecontact portion is disconnected.

[0005] In the meanwhile, a liquid crystal display (LCD) is one of platpanel display devices which are used most widely, and it is a displaydevice that comprises two substrates on which electrodes are formed anda liquid crystal layer interposed therebetween, and that applying theelectrodes makes the liquid crystal molecules in the liquid crystallayer rearranged, thereby adjusting amount of the light transmitted.

[0006] The mainly used LCDs are those that electrodes are formed on twosubstrates respectively and have a thin film transistor switchingvoltages applied to the electrodes.

[0007] In general, on the substrate where a thin film transistor isformed, wire including gate lines transmitting scanning signals and datalines transmitting data signals, and a gate pad and a data pad appliedwith the scanning signals and data lines from external devices totransmit the gate lines and the data lines respectively, are formed, andpixel electrodes electrically connected with the thin film transistorare formed on pixel areas defined by crossing the gate lines and thedata lines.

[0008] Here, it is preferable that an aperture rate of the pixel is sureto be obtained in order to improve display features of the LCDs. Forthis, the wire and the pixel electrodes are made to overlap with eachother, an insulating film made of organic material with a low dielectricconstant is formed therebetween in order to minimize interferences ofsignals transmitted through the wire.

[0009] This method for manufacturing the thin film transistor arraysubstrate for display device requires a process that exposes a pad forreceiving signals from external devices or a process that exposes wirein order to be connected with each other. However, when a lower film isetched to form a contact hole thereon by using an insulating film havingthe contact hole as a mask, the lower film beneath the insulating filmis severely under-cutted, and hence the step coverage of the contactportion becomes bad. This causes problems that the other upper filmsformed later become bad or the wire of the upper films are disconnectedon the contact portion. To solve these problems, it is preferable thatsidewalls of the contact holes in the contact portion are made to bestep-shaped, however, since the organic insulating film must bepatterned several times by a photo etching for this, it has a problemsthat its manufacturing process becomes complex.

[0010] In the meanwhile, a seal line attaching two substrates around theLCD panel and sealing liquid crystal material posed therebetween isformed, and a poor contact is generated if this seal line is formed onthe organic insulating film.

SUMMARY OF THE INVENTION

[0011] An object of the present invention is to provide a contactportion of semiconductor device and a method for manufacturing the same,and a thin film transistor array panel and a method for manufacturingthe same including the same capable of improving the profile of thecontact portion.

[0012] In addition, another object of the present invention is tosimplify a method for manufacturing a thin film transistor array panel.

[0013] Furthermore, another object of the present invention is toprovide a thin film transistor array panel capable of removing the poorcontact.

[0014] To solve these problems, in the present invention, when anorganic insulating film having contact hole is formed, the periphery ofthe contact hole is formed thinner than the other portions. Next, theexposed lower film is etched using the organic insulating film as anetching mask to form contact hole thereon, and thereafter, the thinorganic insulating film is removed by an ashing process to expose thelower film through the contact hole of the organic insulating film.Here, in case under-cut is left under the lower film, a process, whichthe lower film is etched using the organic insulating film as an etchingmask, may be added.

[0015] More in detail, in the contact portion of the semiconductordevice and the method for manufacturing the same according to thepresent invention, first, a first wiring is formed on the substrate, andthe lower film covering the first wiring is formed. Next, aphotosensitive film pattern is formed on the lower film using aphotosensitive organic material, and the lower film is etched using thephotosensitive film pattern as an etching mask, thereby forming thecontact hole for exposing the first wiring. Then, part of thephotosensitive film pattern is removed by an ashing process to exposeborderline of the lower film defining the contact hole, and then asecond wiring connected to the first wiring via the contact hole isformed.

[0016] The lower film may be formed of an insulating film made of SiNxor SiOx, or may be formed of a conducting film made of conductingmaterial.

[0017] In addition, the lower film may be formed of a first insulatinglayer and a second insulating layer, in this case, it is preferablethat, after exposing the borderline of the lower film, the secondinsulating film not blocked by the photosensitive film pattern is etchedto expose the borderline of the first insulating film, wherein thesecond insulating film is formed of a low dielectric insulating filmwhich has a low dielectric constant less than 4.0 and is formed by achemical vapor deposition.

[0018] Here, it is preferable that the photosensitive film patternaround the contact hole is formed thinner than that in theotherportions.

[0019] The contact portion of the semiconductor device and themanufacturing method thereof according to this present invention areequally applicable to a thin film transistor for liquid crystal displayand a manufacturing method thereof.

[0020] First, in a manufacturing method of a thin film transistor arraypanel for liquid crystal display, gate wire, which include a gate line,a gate electrode connected to the gate line and a gate pad connected toone end of the gate line to transmit a scanning signal from a externaldevice to the gate line, are formed on an insulating substate. Next,after forming a gate insulating film and a semiconductor layer, datawire, which include a data line crossing with the gate line, a sourceelectrode connected to the data line and adjacent to the gate electrode,a drain electrode placed opposite to the source electrode in relation tothe gate electrode and a data pad connected to one end of the data lineto transmit an image signal from an external device to the data line,are formed. Next, after depositing a insulating film and forming aphotosensitive organic insulating film pattern, the insulating film isetched using the photosensitive organic insulating film pattern as anetching mask to form a first contact hole for exposing the gate pad orthe data pad. Then, after exposing the borderline of the insulating filmin the first contact hole by the ashing process, an assistant padconnected to the gate pad or the data pad via the first contact hole isformed.

[0021] It is preferable that the organic insulating pattern around thefirst contact hole is formed thinner than that in the other portions.

[0022] The insulating film may formed of a first insulating film and asecond insulating film, in this case, it is preferable that afterexposing the borderline of the insulating film, the second insulatingfilm not blocked by the organic insulating film pattern, and then theorganic insulating film is removed. Here, the second insulating film isa low dielectric insulating film which has a low dielectric constantless than 4.0 and is formed by a chemical vapor deposition.

[0023] Here, it is preferable that the organic insulating film has asecond contact hole for exposing the drain electrode and a pixelelectrode electrically connected to the drain electrode via the secondcontact hole is formed on the same layer as the assistant pad.

[0024] It is preferable that the second contact hole is formed with thefirst contact hole and the organic insulating film pattern around thesecond contact hole is formed thinner than that in the otherportions.

[0025] The data wire and the semiconductor layer may be formed by aphoto etching process using photosensitive patterns whose thickness ispartly different.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1a to FIG. 1e are cross-sectional views showing a method formanufacturing a contact portion of a semiconductor device by a processorder according to a first embodiment of the present invention.

[0027]FIG. 2a to FIG. 2d are cross-sectional views showing a method formanufacturing a contact portion of a semiconductor device by a processorder according to a second embodiment of the present invention.

[0028]FIG. 3 is a thin film transistor array panel for liquid crystaldisplay according to the first embodiment.

[0029]FIG. 4 is a cross-sectional view taken along TV-IV′ of the thinfilm transistor panel shown in FIG. 3.

[0030]FIGS. 5a, 6 a, 7 a and 8 a are arrangement diagrams of the thinfilm transistor panel in the mid-process of manufacturing the thin filmtransistor panel for liquid crystal display according to the firstembodiment of the present invention.

[0031]FIG. 6b is a cross-sectional view taken along VIb-VIb′ shown inFIG. 6a, and shows next step of FIG. 5b.

[0032]FIG. 7b is a cross-sectional view taken along VIb-VIb′ shown inFIG. 7a, and shows next step of FIG. 6b.

[0033]FIG. 8b is a cross-sectional view taken along shown in FIG. 8a,and shows next step of FIG. 7b.

[0034]FIG. 8c is a cross-sectional view showing an area where a sealline will be formed on the thin film transistor array panel for liquidcrystal display according to the first embodiment.

[0035]FIG. 9 is a cross-sectional view taken along shown in FIG. 8b, andshows next step of FIG. 8b.

[0036]FIG. 10a is a cross-sectional view taken along shown in FIG. 8a,and shows next step of FIG. 9b.

[0037]FIG. 10b is a cross-sectional view showing next step of FIG. 8c.

[0038]FIG. 11 is an arrangement view of a thin film transistor panel forliquid crystal display according to a second embodiment.

[0039]FIG. 12 and FIG. 13 are cross-sectional views taken along XII-XII′and XIII-XIII′ of the thin film transistor shown in FIG. 11.

[0040]FIG. 14a is an arrangement view of thin film transistor in a firststep, manufactured according to the second enmbodiment of the presentinvention.

[0041]FIG. 14b and FIG. 14c are cross-sectional views taken alongXIVb-XIVb′ and XIVc-X IVc′ shown in FIG. 14a, respectively.

[0042]FIG. 15a and FIG. 15b are cross-sectional views taken alongXIVb-XIVb′ and XIVc-XIVc′ shown in FIG. 14a, respectively, and showsnext step of FIG. 14b and FIG. 14c.

[0043]FIG. 16a is an arrangement view of thin film transistor of nextstep of FIG. 15a and FIG. 15b.

[0044]FIG. 16b and FIG. 16c are cross-sectional views taken alongXVIb-XVIb′ and XVIc-XVIc′ shown in FIG. 16a, respectively.

[0045]FIGS. 17a, 18 a, 19 a and FIGS. 17), 18 b, 19 b arecross-sectional views taken along XVIb-XVIb′ and XVIc-XVIc′ and shown inFIG. 16, respectively, and show next step of FIG. 16b and FIG. 16c by aprocess order.

[0046]FIG. 20a is an arrangement view of thin film transistor in nextstep of FIG. 19a and FIG. 19b.

[0047]FIG. 20b and FIG. 20c are cross-sectional views taken alongXXb-XXb′, and shown in FIG. 20a, respectively.

[0048]FIG. 21a and FIG. 21b are cross-sectional views taken alongXXb-XXb′ and XXc-XXc′ and shown in FIG. 20a, respectively, and show nextstep of FIG. 20b and 20 c by a process order.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] A contact portion of semiconductor device and a method formanufacturing the same, and a thin film transistor array panel and amethod for manufacturing the same including the contact portion ofsemiconductor device and the method for manufacturing the same accordingto embodiments of the present invention will be described in detain withreference to accompanying drawings so that those skilled in the artpractice easily.

[0050] First, a contact portion and a method for manufacturing the samewill be described according to an embodiment of the present invention.

[0051] In general, as a semiconductor device is more integrated, it ispreferable that an area of thereof is made to be optimized or its wiringis formed of multi-layers for the purpose of assisting a pad connectedto signal lines for receiving signals from external devices. Asemiconductor device according to an embodiment of the present inventionincludes an interlayer insulating film with a low dielectric constantfor the purpose of minimizing interferences of signals transferredthrough wire, and an organic film made of an organic material that asmoothing feature is excellent. Here, a contact hole needs to be formedon the insulating layer in order to electrically connect the wirebetween layers with each other, and when the interlayer insulating filmis etched to form the contact hole, a manufacturing method according toan embodiment of the present invention makes a periphery of the contacthole of the organic insulating film thinner than the other portionsthereof for the purpose of removing the under-cut generated in thecontact portion. Next, a lower film is etched using the organicinsulating film as a etching mask, and then an ashing process isperformed to remove the thin insulating film, thereby exposing the lowerfilm.

[0052]FIG. 1a to FIG. 1e are cross-sectional views showing a method formanufacturing a contact portion of a semiconductor device by a processorder according to a first embodiment of the present invention, and FIG.2a to FIG. 2d are cross-sectional views showing a method formanufacturing a contact portion of a semiconductor device by a processorder according to a second embodiment of the present invention.

[0053] In a manufacturing method of a contact portion of a semiconductordevice according to the first embodiment of the present invention, asshown in FIG. 1a, first, a lower insulating film 310 made of SiNx orSiOx is deposited on a substrate 100 where a first wiring 200 is formed,and then, as an upper insulating film, an organic insulating film 320with a low dielectric constant and made of a photosensitive organicmaterial is coated thereon, thereby forming a interlayer insulatingfilms 300.

[0054] Next, as shown in FIG. 1b, a transmittance area is formed on aportion corresponding to a contact hole 330 in order to forming thecontact hole 330 for exposing the first wiring 200, and for the purposeof adjusting a light transmittance, around the transmittance area, aslit or a lattice type pattern is mainly formed, or the organicinsulating film pattern, which is exposed and developed using a maskwith a semi-transmittance area where a sen-transparent film is formed tohave the contact hole 330 for exposing the lower insulating film 310 onthe first wiring 200, is formed. In this regard, by exposing anddeveloping the organic insulating film 320 using the mask with asemi-transmittance area, the organic insulating film 320 around theopening portion is left to be thinner than that in the other portions.This will be described in detail in a manufacturing method of a thinfilm transistor panel for liquid crystal display according to a fourthembodiment of the present invention which manufactures the thin filmtransistor for liquid crystal display using four masks. It is preferablethat the thickness of the organic insulating film 320 around the contacthole 30 is not more than 2,000 Å in consideration of the thicknessremoved in the asking process thereafter.

[0055] Then, as shown in FIG. 1c, the lower insulating film 310 exposedthrough the contact hole 330 is etched to expose the first wiring 200.Here, since reaction of an etching gas is performed isotropically in theprocess of etching even using a dry etching, let alone a wet etching,the lower insulating film 310 is etched to the organic insulating filmpattern 320, and hence an under-cut is generated.

[0056] Next, as shown in FIG. 1d, an ashing process is performed toremove part of the organic insulating film pattern 320 which is aphotosensitive film. The organic insulating film, which the periphery ofthe contact hole 330 is formed thinner than the other portions, iscompletely removed to make the border line of the lower insulating filmbe exposed.

[0057] Then, as shown in FIG. 1e, a conducting material is deposited onthe organic insulating film pattern 320, and patterned by a photoetching process using a mask, thereby forming a second wiring 400electrically connected to the first wiring 200 via the contact hole 330.

[0058] In the contact portion of the semiconductor device and themanufacturing thereof according to the first embodiment of the presentinvention, when the interlayer insulating film is made of an organicmaterial and the contact hole for exposing the first wiring 200 isformed, by forming the sidewall of the organic insulating film 320step-shaped and performing the ashing process after etching the lowerinsulating film 310, the under-cut structure generated under the organicinsulating film of the contact portion is removed. This can prevent thesecond wiring from disconnecting with the first wiring, and improve theprofile of the second wiring 400 in the contact portion smooth.

[0059] Although the lower insulating film 310 under the organicinsulating film 320 has been described as an example, this is equallyapplicable to case that a lower film of the organic insulating film 320is also a conducting film. That is, as in the method the presentinvention for manufacturing of the contact portion, in case theconducting film under the organic insulating film is etched, when theconducting film is etched to the lower part of the organic insulatingfilm to form an under-cut on the contact portion, by forming theperiphery of the contact hole thinner and removing this by the ashingprocess to expose the conducting film on the contact portion, theunder-cut thereon can be removed.

[0060] In the meanwhile, in a contact hole of a semiconductor device anda manufacturing thereof according to a second embodiment of the presentinvention, as shown in FIG. 2a, when an interlayer insulating film 300is made of a dual layer including a lower insulating film 310 and anupper lower insulating film 320, and the insulating film 300 ispatterned using the organic insulating film 320 (See FIG. 1b) as aphotosensitive pattern of an etching mask to form the contact hole forexposing a first wiring 200, the lower insulating film 310 is etched tothe lower part of the upper insulating film to be able to generate anunder-cut. Also, in this case, as shown in FIG. 2a, part of thephotosensitive film pattern 500 around the contact hole 330 is formedthinner than that in the otherportions.

[0061] Next, part of the photosensitive film pattern 500 around thecontact hole 330 formed thinner than that in the otherportions isremoved by performing an ashing process. Here, it is preferable that anetching condition has an etching selectivity of the upper insulatingfilm 320 and the lower insulating film 310.

[0062] Next, as shown in FIG. 2d, by removing the photosensitive filmpattern 500, depositing a conducting material on the upper insulatingfilm 320, and patterning it by a photolithography process using a mask,a second wiring 400 electrically corrected to the first wiring 200 isformed.

[0063] In the contact portion of the semiconductor device and themanufacturing thereof according to the second embodiment of the presentinvention, when the interlayer insulating film is made of an organicmaterial and the contact hole exposing the first wiring 200 is formed,by forming the photosensitive film defining the contact hole step-shapedand performing the ashing process after etching the lower insulatingfilm 330 to remove a part of the photosensitive film, and the upperinsulating film is etched again using the photosensitive mask as a mask,thereby removing the under-cut structure generated in the contactportion. This can prevent the second wiring 400 from disconnecting withthe first wiring 200, and improve the profile of the second wiring 400in the contact portion smooth.

[0064] In the meanwhile, the contact portion of the semiconductor deviceand the manufacturing method thereof can be also applicable to a thinfilm transistor array substrate for liquid crystal display and amanufacturing method thereof. Here, it will be described that thecontact portion of the semiconductor and the manufacturing methodthereof according to the first embodiment of the present invention isapplied to a thin film transistor for liquid crystal display and amanufacturing method thereof according to the first embodiment of thepresent invention, and that the contact portion of the semiconductor andthe manufacturing method thereof according to the second embodiment ofthe present invention is applied to a thin film transistor for liquidcrystal display and a manufacturing method thereof according to thesecond embodiment of the present invention.

[0065] First, a structure of a thin film transistor panel for liquidcrystal display according to a first embodiment of the present inventionwill be described in detail with reference to FIG. 3 and FIG. 4.

[0066]FIG. 3 shows a thin film transistor panel for liquid crystaldisplay according to a first embodiment of the present invention, andFIG. 4 is a cross-sectional view taken along the IV-IV′ of the thin filmtransistor shown in FIG. 3.

[0067] Gate wire including aluminum-based metal material having a lowresistance are disposed on an insulating substrate 10. The gate wireinclude gate lines 22 extending in a horizontal direction, gate pads 24connected to one end of the gate lines 22 to transmit gate signals froman external device to the gate lines, and gate electrodes 26 of the thinfilm transistor connected to the gate lines 22

[0068] The gate wire 22, 24 and 26 are preferably formed ofaluminum-based single layer, however, they may be formed of more thantwo layers. In case of forming more than two layers, it is preferablethat one layer is formed of a material with a low resistance and theother layers are formed of chromium-based or molybdenum-based materialsthat are excellent in a contact characteristic with other materials suchas ITO, IZO or the substrate.

[0069] A gate insulating film 30 made of SiNx, etc., covers the gatewire 22, 24 and 26 on the substrate 10, and has a contact hole 74 forexposing the gate pad 24 with a passivation layer 70 formed later.

[0070] A semiconductor layer made of semiconductor such as amorphoussilicon, etc. , is formed on the gate insulating layer of the gateelectrode 24, and, ohmic contact layers 55 and 56 made of material suchas n+hydrogenated amorphous silicon doped with high-concentratedsilicide or n-type impurity, are formed on the semiconductor layer 40,each of which is formed divided into two parts as seen in the center ofgate pad 26.

[0071] Data wire 62, 64, 65 and 66 made of metals, for example, Al or Alalloy, Mo or MoW alloy, Cr, Ta, etc., or of conductor, are formed on theohmic contact layers 55 and 56 and the gate insulating film 30. The datawire include data lines disposed in a vertical direction, crossing withthe gate lines 22 to define the pixels, source electrodes 62 which arebranches of the data lines and extend to upper side of the ohmic contactlayer 55, data pads 68 connected to one end of the data lines 62 andreceiving image signals from an external device, and drain electrodes 66separated from the source electrodes and formed on the ohmic contactlayer 56 disposed opposite to source electrodes 65 in relation to thegate electrodes 26. In the meanwhile, the data wire may include aconductor pattern for storage capacitor which overlaps the ate lines 22and has a purpose of securing a storage capacity.

[0072] The data wire 62, 64, 65, 66 and 68 may be formed of single layermade of Al or Al alloy too, and formed of more than dual layers. In caseof being formed of dual layers, it is preferable that one layer isformed of material with a low resistance and the other layers are formedof material whose the contact characteristic is excellent. As such anexample, there are Cr/Al(or Al alloy) or Al/Mo, and in this regards, Crfilm has a function to prevent Al film or Al alloy film from beingdispersed into Si layers 40, 55 and 56, which also has a function as acontact portion for securing contact characteristics between the datawire 62, 64, 65, 66 and 68 and pixel electrodes formed later.

[0073] On the data wire 62, 64, 65, 66 and 68 and the semiconductorlayer 40 not blocked by those, the passivation layer 70 made of SiNx,and an organic insulating film made of acril-based photosensitiveorganic material having a smoothing characteristic and a low dielectricconstant, are formed. On the passivation layer 70, the conductor patternfor storage capacitor 64, the drain electrodes 66 and the contact holes72, 76 and 78 for exposing the data pads 68 are formed respectively, andalso, the contact hole 74 for exposing the gate pads 24 with the gateinsulating film 30 is formed. Here, the borderline of the organicinsulating film in the contact holes 72 and 76 is formed on thepassivation film 70 to expose the borderline of the passivation film 70or the gate insulating film 30, and hence the sidewalls defining thecontact holes 72 and 76 become step-shaped. In addition, it ispreferable that the organic insulating film 75 is removed from the padportion where the gate pads and the data pads are formed, and thecontact hole 74 for exposing the gate pad 24 is formed larger than thegate pad 24.

[0074] On the organic insulating film 75, pixel wire, which includepixel electrodes 82 connected to the drain electrodes 66 via the contacthole 76 and located in the pixels, and assistant gate pads 84 andassistant data pads 88 each connected to the gate pads 24 and the datapads 68 via the contact holes 74 and 78, and are made of ITO (indium tinoxide) or IZO (indium zinc oxide) which is a transparent conductingmaterial, are formed. In this regard, as described above, in the contactportion, the sidewall of the passivation film 70 or the organicinsulating film 75, a lower insulating film has a step-shaped and has nounder-cut structure, and therefore this can prevent the pixelelectrodes, the assistant gate pads 84 and the assistant data pads 88from being disconnected. Here, since the organic insulating film 75 isremoved from the pad portion, the assistant gate pads 84 and theassistant data pads 88 are formed only to the upper side of thepassivation film 70. The reason is that the organic insulating film 75is very poor of adhesive strength, chemical-resisting quality, hardness,mechanical intensity, stress, etc., compared with a passivation filmmade of SiNx. Therefore, in case that the organic insulating film 75exists in the pad portion, when a driving integrated circuit is directlymounted on a thin film transistor for liquid crystal display using COG(chip on glass) manner or a film where a driving integrated circuit ispacked by TCP or COF manner is attached thereto, an adhesive strength ofthe pad portion is poor and, in turn, this cause a poor adhesion. Inaddition, when rework is required to improve the poor adhesion, ananisotropy conducting film should be removed from the pad portion afterthe driving integrated circuit or the film is detached therefrom, andhere, if the organic insulating film remains behind, this causes aproblem of a surface damage of the pad portion or an ITO filmpeeling-off between the organic insulating film and the assistant films84 and 88. Thus, completely removing the organic insulating film fromthe pad portion can improve the adhesive strength between the pad andthe driving integrated circuit or the film, and can practice the reworkvery easily.

[0075] As shown in FIGS. 3 and 4, the pixel electrodes overlaps the gatelines 22 to form storage capacitors, and here, when the storagecapacities are deficient, independent wires for storage capacitiesseparated from the gate wire 22, 24 and 26 may be added to the samelayer as the gate wire 22, 24 and 26.

[0076] Then, the method for manufacturing a thin film transistor forliquid crystal display according to the first embodiment of the presentinvention will be described in detail with reference to FIGS. 3 and 4,and FIG. 5a to FIG. 10.

[0077] First, as shown in FIGS. 5a and 5 b, on a substrate 10, aconducting material whose contact characteristic is excellent or whichhas resistance such as Al or Al alloy, and Ag or Ag alloy, is depositedand patterned to form gate wire including gate lines 22, gate electrodes26 and gate pads .4.

[0078] Next as shown in FIGS. 6a and 6 b, three-layer film, a gateinsulating film 30, a semiconductor layer 40 made of an amorphoussilicon and a doped amorphous silicon layer 50, is depositedsuccessively, and the semiconductor layer 40 and the doped amorphoussilicon layer 50 are patterned by a patterning process using a mask,thereby forming the semiconductor layer 40 and the ohmic contact layer50 on the gate insulating film 30 disposed opposite to the gateelectrode 24. In this regard, as shown in FIGS. 6a and 6 b, thesemiconductor layer 40 and the ohmic contact layer 50 are formed alongthe data lines formed later.

[0079] Next, as shown in FIGS. 7a and 7 b, a conducting material such asCr, Mo or Mo alloy, Al or Al alloy, or Ag or Ag alloy is deposited, andthen, patterned by a photo etching using a mask to form data wireincluding data lines 62 crossing with the gate lines, source electrodes65 connected to the data lines 62 to extend to upper side of the gateelectrodes 926, data pads 68 connected to one end of the data lines 62,drain electrodes 66 separated from the source electrodes 65 and disposedopposite thereto, and conductor patterns for storage capacitors.

[0080] Next, the amorphous silicon layer pattern 50 not blocked by thedata wire 62, 64, 65, 66 and 68 is etched to be divided into two partscentering around the gate electrode 26, and simultaneously thesemiconductor layer 40 interposed between the doped amorphous siliconlayers 55 and 56 is exposed. Then, it is preferable to practice anoxygen plasma in order to stabilize a surface of the exposedsemiconductor 40.

[0081] Next, as shown in FIGS. 8a and 8 b, the passivation layer 70 madeof SiNx is deposited no more than 2,000 Å thick, preferably, 1,000 Åthick, and the organic insulating film 75 made of a organic insulatingmaterial with a photosensitivity is formed in a range of 2˜4 μm thickthereon, and, first, only the organic insulating film 75 is exposed anddeveloped by a photo process using a mask to form contact holes 72, 74,76 and 78 on the conductor pattern for the storage capacitor 64, thegate pad 24, the drain electrode 66 and the data pad 68, respectively. Apattern of slit type or a lattice type, or a semi-transmittance areamade of a semi-transparent film is formed so that a light transmittancearound transmittance area of the mask is reduced, and the organicinsulating film 75 around the pad portion where several pads 24 and 68are formed or the contact holes 74 and 78 is formed thinner than that inthe otherportions, preferably, insulating film a range of 1,000˜5,000 Åthick. Of course, in this regard, the organic insulating film 75 aroundthe contact holes 72 and 76 for exposing the drain electrode 66 and theconductor pattern for the storage capacitor 64 may be formed with astep-shaped structure that its thickness is thinner than the otherportions.

[0082] In the meanwhile, a seal line is formed on one panel of them forthe purpose of attaching two panels for liquid crystal display andsealing the liquid crystal material interposed therebetween, and sincethe adhesive strength of the seal line becomes weak on forming the sealline on an organic insulating film 75, a poor contact is generatedbetween the two panels. It is preferable that, in order to prevent thepoor contact, the organic insulating film 75 is removed from an areawhere the seal line will be formed later, and that, for this, as shownin FIG. 8c, by forming a semi-transmittance area on the mask of the areawhere the seal line will be formed, the organic insulating film 75 isformed thinner than the other portions.

[0083] Here, a method for adjusting the thickness of a photosensitivefilm will be described in detail later when a method for manufacturing athin film transistor array panel for liquid crystal display using fourmasks is describe.

[0084] Next, as shown in FIG. 9, the passivation film 70 and the gateinsulating film 30 exposed by the contact holes 72, 74, 76 and 78 usingthe organic insulating film 75 as an etching mask are etched and so theconductor pattern for storage capacitor 64, the gate pattern 24, thedrain electrode 66 and the data pad 68 are exposed. Here, a method toetch the passivation film 70 is preferably a dry etching, and SF6+O₂ orCR4+O₂ is used as a dry etching gas. When the passivation film and thegate insulating film 30 are etched, as seen in drawings, they are etchedto lower side of the organic insulating film 75 to cause an under-cut,though using a dry etching.

[0085] Next, as shown in FIG. 10a, an ashing process is performed toremove part of the organic insulating film 75, so that, in the padportion, the passivation layer 70 around the contact holes 74 and 78 isexposed by removing the organic insulating film 75 having a smallthickness, and in the contact holes 72 and 76, the gate insulating film30 and the passivation film 70 are exposed by the organic insulatingfilm 75. This enables the under-cut structure generated in the contactportion to be removed. Here, as shown in FIG. 10b, the passivation film70 made of SiNx is exposed in an area for forming the seal line. In thisway, the seal line formed later can be formed on the passivation layerto improve the adhesive strength between the two panels for liquidcrystal display.

[0086] Finally, as previously shown in FIGS. 3 and 4, by depositing anITO or an IZO and performing a patterning using a mask, the conductorpattern for storage capacitor 64 and the pixel electrode 82 connected tothe drain electrode 66 through the contact holes 72 and 76 are eachformed, and also the assistant gate pad 84 and the assistant data pad 88each connected to the gate pad 24 and the data pad 68 through thecontact holes 74 and 78 are each formed. As described above, theunder-cut structure generated in the contact portion is removed byforming the organic insulating film 75 around the contact holes 72, 74,76 and 78 thinner and performing an ashing process, so that the pixelelectrode 82, the assistant gate pad 84 and the assistant data pad 88can be prevented from being disconnected and the profile of them can beformed smooth. Here, as seen in drawings, the assistant gate pad 84 andthe assistant data pad 88 are formed to upper side of the passivationfilm 70. When the assistant gate pad 84 or the assistant data pad 88needs to cover lower metal pads 24 and 68 completely for the purpose ofpreventing the pads 24 and 68 from being corroded and is formed to theupper side of the passivation film 70, there are advantages of animprovement of the adhesive strength between the assistant pads 84 and88 and an enlargement of the assistant pads 84 and 88.

[0087] In the method for manufacturing the thin film transistor forliquid crystal display according to the first embodiment, as describedabove, although the manufacturing method thereof described using fivemasks, it is equally applicable to a manufacturing method thereof usingfour masks. This will be described in detail with reference to drawings.It will be described that a method for manufacturing a semiconductordevice according to a second embodiment, which uses an organicinsulating film not as an interlayer insulating film but as aphotosensitive film pattern and adds a low dielectric CVD insulatingfilm which has a low dielectric constant less than 4.0 and is formed bya chemical vapor deposition, is applied.

[0088] First, referring to FIG. 11 to FIG. 13, a unit pixel structure ofa thin film transistor array panel for liquid crystal display formed byusing four masks according to an embodiment of the present inventionwill be described in detail.

[0089]FIG. 11 is an arrangement view of a thin film transistor panel forliquid crystal display according to a second embodiment, and FIG. 12 andFIG. 13 are cross-sectional views taken along XII-XII′ andXIII-XIII-XIII′ of the thin film transistor shown in FIG. 11.

[0090] Like the first embodiment, gate wire, which include gate lines 22made of conducting material with a low resistance such as, Al or Alalloy, or Ag or Ag alloy, etc., gate pad 24 and gate electrode 26, areformed on an insulating substrate 10. The gate wire also include astorage electrode 28 which is parallel with the gate lines 22 on thesubstrate 10 and is applied with a voltage such as a common electrodevoltage inputted to a common electrode placed in an upper plate from anexternal device. The storage electrode 28 overlaps a conductor patternfor storage capacitor 68 connected to a pixel electrode described laterto form a storage capacitor for improving charge reservation ability ofthe pixel, and if a storage capacity generated by overlapping the pixelelectrode 82 described later with the gate line 22 is enough, thestorage capacitor may not be formed.

[0091] A gate insulating film 30 made of SiNx, etc., is formed on thegate wire 22, 24, 26 and 28 to cover these.

[0092] Semiconductor patterns 42 and 48 made of a semiconductor such asa hydrogenated amorphous silicon is formed on the gate insulating film30, and ohmic contact layer pattern or middle layer patterns 55, 56 and58 made of an amorphous silicon which n-type impurity such as P is dopedwith high concentration are formed on the semiconductor patterns 42 and48.

[0093] Data wire made of an aluminum-based conducting material with lowresistance are formed on the ohmic contact layer patterns 55, 56 and 58.The data wire include data line portion comprising data line 62, a datapad 68 connected to one end of the data line 62 to be applied with imagesignals from an external device, and a source electrode 65 of thin filmtransistor which is branch of the data line 62. The data wire alsoinclude a drain electrode 66 of thin film transistor separate from thedata line portion 62, 68 and 65 and placed opposite to the sourceelectrode 65 in relation to the gate electrode or channel C, and aconductor pattern for storage capacitor 64 placed over the storageelectrode 28. In case the storage electrode is not formed, neither isthe conductor pattern formed.

[0094] The contact layer patterns 55, 56 and 58 play a part in reducingthe contact resistance between the semiconductor patterns 42 and 48 andthe data wire 62, 64, 65, 66 and 68 under themselves, and have perfectlythe same shapes as the data wire 62, 64, 65, 66 and 68. That is, themiddle layer pattern 55 in the data portion has the same shape as thedata portion 62, 65 and 68, the middle layer pattern for the drainelect-ode 56 has the same shape as the drain electrode 66, and themiddle layer pattern for the storage capacitor 58 has the same shape asthe conductor pattern for the storage capacitor 68.

[0095] In the meantime, the semiconductor patterns 42 and 48 have thesame shapes as the data wire 62, 64, 65, 66 and 68 and the ohmic contactlayer patterns 55, 56 and 58 except the channel portion of the thin filmtransistor. In detail, the semiconductor pattern for storage capacitor48, the conductor pattern for storage capacitor 68 and the contact layerpattern for storage capacitor 58 have the same shapes, but thesemiconductor pattern for thin film transistor 42 has the slightlydifferent shape from the data wire and the contact layer patterns. Inother words, the data line portion 62, 68 and 65 in the channel portionof the thin film transistor, in particular, the source electrode 65 andthe drain electrode 66 are separate, and the middle layer 55 of the dataline portion and the contact layer pattern for drain electrode 56 arealso separate, however, the semiconductor pattern for thin filmtransistor 42 is not disconnected but connected in this place to form achannel of thin film transistor.

[0096] Unlike the first embodiment, on the data wire 62, 64, 65, 66 and68, the passivation film made of SiNx, and the low dielectric insulatingfilm 73 that has a low dielectric constant less than 4.0 and is formedby a chemical vapor deposition, are formed, and these have the contactholes 76, 78 and 72 for exposing the drain electrode 66, the data pad 68and the conductor pattern for storage capacitor 64, also have thecontact hole 74 for exposing the gate insulating film 30 and the gatepad 24. In this regard, like the first embodiment, the low dielectricinsulating film 73 is removed from the pad portion to expose thepassivation film 70, and the borderline of the passivation film or thegate insulating film as the lower insulating film is exposed in thecontact holes 72 and 76, and so the sidewalls of the contact holes 72and 76 have the step-shaped.

[0097] On the low dielectric insulating film 73, a pixel electrode 82,which is applied with image signals from the thin film transistor togenerate an electric field in cooperation with electrodes in the upperplate, are formed. The pixel electrode 82 is made of a transparentconducting material such as an IZO or an ITO, and is connected to thedrain electrode 66 via the contact hole 76 to receive the image signals.The pixel electrode 82 also overlaps the adjacent gate line 22 and dataline 62 to increase the aperture rate, however, alternately not. Inaddition, the pixel electrode 82 is connected to the conductor patternfor storage capacitor 64 via the contact hole 72 to transmit the imagesignals thereto. On the gate pad 24 and the data pad 68, the assistantgate pad 84 and the assistant data pad 88 connected thereto via thecontact holes 74 and 78 each. These play a part in complementing theadhesivity of the pads 94 and 68 and external circuit devices andprotecting the pads, whether these are applied or not is selective.

[0098] As described above, also in the thin film transistor array panelaccording to the second embodiment, the sidewalls have step-shapedstructure by exposing the protecting film 70 as a lower insulating film,and since the passivation film 70 in the pad portion is exposed not togenerate a under-cut structure in the contact portion, the pixelelectrode 82, the assistant gate pad 84 and the assistant data pad 88can be prevented from being disconnected. Moreover, the assistant gatepad 84 and the assistant data pad 88 are formed to the upper side of thepassivation film 70.

[0099] Although the transparent ITO or IZO has been described asexemplary materials of the pixel electrode 82, opaque conductingmaterials may be used in case of reflective liquid crystal displays.

[0100] A method for manufacturing a thin film transistor for liquidcrystal display having structures of FIG. 11 to FIG. 13 using four maskswill be described in detail with reference to FIG. 11 to FIG. 13 andFIG. 14a to FIG. 20c.

[0101] First, as shown in FIGS. 14a to 14 c, in the same manner as thefirst embodiment, a conducting material for gate wire is deposited, andthen the gate wire including a gate line 22, a gate pad 24, a gateelectrode 26 and a storage electrode 28 are formed on a substrate 10 bya photo etching process using a first mask.

[0102] Next, as shown in FIGS. 15a and 15 b, a gate insulating film 30,a semiconductor layer 40 and a middle layer 50 are deposited insuccession 1,500 Å-5,000 Å, 500 Å-2,000 Å and 300 Å-600 Å thick,respectively, and then, a conductor layer 60 made of a conductingmaterial for data wire with a low resistance is deposited 1,500 Å-3,000Å thick by way of a sputtering, etc., and thereafter, a photosensitivefilm 110 is coated 1 μm-2 μn thick thereon.

[0103] Then, after a light is irradiated to the photosensitive film 110through a second mask and developed, the photosensitive patterns 112 and114 are formed as shown in FIGS. 16b and 16 c. The channel portion C ofthin film transistor of the photosensitive film patterns 112 and 114,i.e., the first portion 114 posed between the source electrode 65 andthe drain electrode 66 is made to be thinner than the data wire portionA, i.e., the second portion 112 posed in the portion where the data wire62, 64, 66 and 68 will be formed, and all the photosensitive films inthe other portions are removed. Here, the ratio of the thickness of thephotosensitive film 114 left in the channel portion C and that of thephotosensitive film 112 left in the data wire portion A are made to bevaried depending on a process condition of etching process describedlater, and it is preferable that the thickness of the first portion 114is less than a half, for example, less than 4,000 Å of that of thesecond portion

[0104] As above, there may be several methods for varying the thicknessof the photosensitive film depending on positions, and the pattern of aslit type or a lattice type is formed on the mask, or, thesemi-transmittance area is formed thereon by using a semi-transparentfilm, in order to adjust an amount of a light transmittance in an areaA. Of course, this method is equally applicable to the case that theorganic insulating film (75, see FIG. 7) around the contact holes 72,74, 76 and 78 is formed thinner than that in the other portions, and itis preferable that its thickness is adjusted in consideration of anashing process.

[0105] In this regard, it is preferable that a line width of thepatterns or an interval of the pattern placed among the slits, that is,the width of the slit is smaller than a resolution used at exposure, incase of using a semi-transparent film, thin films with differenttransmittances or different thickness may be used to adjust thetransmittance on manufacturing masks.

[0106] When a light is irradiated to the photosensitive film throughsuch masks, high molecules in the portion exposed directly to the lightare completely decomposed, and high molecules in the portion where theslit pattern or the semi-transparent film is formed are not completelydecomposed because an amount of a light irradiation is smaller, and highmolecules in the portion blocked by a light-shield film is hardlydecomposed. Next, when the photosensitive film is developed, the portionwhere the high molecules are not decomposed is left, and the portionwhere the light is irradiated a little is left thinner than that in theportion where the light is not irradiated at all. Here, since themolecules all are decomposed in case exposure time is made to be long,it is necessary not to do so.

[0107] A photosensitive film made of a material capable of reflowing isused and exposed with a mask whose portions transmitting a lightcompletely and not transmitting a light completely is divided, and then,developed and reflowed to make part of the photosensitive film flow tothe portion where the photosensitive film does not remain, andconsequently, such thinner photosensitive film 114 may be formed.

[0108] Next, the photosensitive film 114 and the lower films thereof,i.e., the conductor layer 60, the middle layer 50 and the semiconductorlayer 40 are etched. In this case, the data wire and the lower filmsthereof have to be left the same in the data wire portion A, only thesemiconductor layer has to be left in the channel portion C, and theabove three layers 60, 50 and 40 all have to be removed to expose thegate insulating film 30 in the other portions B.

[0109] First, as shown in FIG. 17a and 17L), the conductor layer 60exposed in the other portions B is removed to expose the middle layer 50thereof. Both a dry etching and a wet etching are used in this process,and here, they are preferably performed under the condition that theconductor layer 60 is etched and the photosensitive film patterns 112and 114 are hardly etched. However, it is not easy that the condition,which only the conductor layer 60 is etched and the photosensitive filmpatterns 112 and 114 is not etched, is found in the dry etching, andtherefore it may be performed under the condition that thephotosensitive patterns 112 and 114 are etched, too. In this case, thefirst portion 114 is made to be thicker than in the wet etching, andhence it has to be prevented that the first portion 114 is so removedthat the lower conductor layer 60 is exposed.

[0110] Here, in case that the conducting material for data wire is Al orAl alloy, either will do of the dry etching and the wet etching.However, in case of Cr, since the first portion 114 is not removed well,the wet etching had better be used, and CeNHO₃ is used as an etchant,and also the dry etching may be used when Cr is deposited very thinly toan extent of 500 Å thick.

[0111] In this way, as shown in FIG. 17a and FIG. 17b, the conductorlayer o() 60 in the channel portion C and the data wire B, that is, onlythe conductor pattern for source/drain 67 and the conductor pattern forstorage capacitor 64 are left and the conductor pattern 60 in the otherportions B are removed to expose the middle layer 50 thereof. Here, theremaining conductor patterns 67 and 64 are the same forms as the datawire 62, 64, 65, 66 and 68 except the point that the source electrode 65and the drain electrode 66 are not disconnected but connected.Furthermore, when the dry etching is used, the photosensitive patterns112 and 114 are etched to some extent of thickness.

[0112] Next, as shown in FIG. 18a and FIG. 18b, the exposed middle layer50 and the lower semiconductor layer 40 thereof in the other portions Bare simultaneously removed with the first portion by a dry etching. whenthe conductor pattern 67 is etched by a dry etching, the middle layer 50and the semiconductor layer 40 are sequentially etched by a dry etching,which is proceeded with an in-situ. The etching of the middle layer 50and the semiconductor layer 40 should be performed under the conditionthat the photosensitive film patterns 112 and 114, the middle layer 50and the semiconductor layer 40 (the middle layer and the semiconductorlayer hardly have etching selectivity) are simultaneously etched and thegate insulating film 30 is not etched, especially it is preferable thatthe etching ratio of the photosensitive film patterns 112 and 114 andthe semiconductor pattern 40 is almost the same condition. When theratio of the photosensitive film patterns 112 and 114 and thesemiconductor pattern 40 is the same, the thickness of the first portion114 is the same as, or less than the sum of that of the semiconductorlayer 40 and the middle layer 50.

[0113] In this way, as shown in FIGS. 18a and 18 b, the conductor layersin the channel portion C and the data wire B, that is, only theconductor pattern for source/drain 67 and the conductor pattern forstorage capacitor 64 is left and the conductor layers 60 in the otherportions B all are removed. Furthermore, the first portion 114 in thechannel portion C is removed to expose the conductor pattern forsource/drain, and the middle layer 50 and the semiconductor layers 40 inthe other portions B are removed to expose the lower gate insulatingfilm 30 thereof. In the meanwhile, the second portion 112 in the datawire A is also etched, and hence it becomes thinner. Moreover, theconductor patterns 42 and 48 are completed in this procedure.

[0114] The reference numerals 57 and 58 indicate the lower middle layerpattern of the conductor pattern for source/drain 67 and the lowermiddle layer pattern of the conductor pattern for storage capacitor 64,respectively. Here, the conductor pattern for source/drain in thechannel portion C may be exposed by a separate PR etch back process,and, under the condition that a photosensitive film is etchedsufficiently, the PR etch back process may be omitted.

[0115] Then, photosensitive film remnants left in the surface of theconductor pattern for source/drain in the channel portion C are removedthrough an ashing process.

[0116] Next, as shown in FIG. 19a and 19 b, the conductor pattern forsource/drain 67 and the lower middle pattern for source/drain 57 thereofin the channel portion C are etched to be removed. Here, the etching ofboth of them may be done using only a dry etching, the conductor patternfor source/drain is etched by a wet etching, and the middle layerpattern 57 is etched by a dry etching. In this regard, as shown in FIG.15, part of the semiconductor pattern 42 is removed and thus itsthickness becomes smaller, and here, the second portion 112 of thephotosensitive film pattern is also etched to some extent of thickness.This etching is performed under the condition that the gate insulatingfilm 30 is not etched, and it is preferable that the photosensitive filmpattern is thick so that the second portion 12 is etched not to exposethe lower data wire 62, 64, 65, 66 and 68 thereof.

[0117] In this way, while the source electrode 65 and the drainelectrode 66 are isolated, the data wire 62, 64, 65, 66 and 68 and thecontact layer patterns 55, 56 and 58 thereof are completed.

[0118] Finally, the second portion 112 of the photosensitive film leftin the data wiring portion A is removed. However, the second portion 112may be removed after the conductor pattern 67 for source/drain in thechannel portion C is removed and before the lower middle layer pattern57 thereof is removed.

[0119] After the data wire 62, 64, 65, 66 and 68 are formed in such way,as shown in FIG. 20a to FIG. 20c, SiNx is deposited by a chemical vapordeposition to form the passivation layer 70, and SiOC or SiOF with a lowdielectric constant which is less than 4.0 is deposited thereon by achemical 10 vapor deposition to form the low dielectric insulating film73. Next, after an organic insulating film is formed on the lowdielectric insulating film 73 by a spin coating, it is exposed anddeveloped using a third mask to form the photosensitive pattern 250,and, by using this as an etching mask, the contact holes 72, 74, 76 and78 for exposing the conductor pattern for storage capacitor 64, the gatepad 24, the drain electrode 66 and the data pad 6S are formed. Also inthis regard, the passivation film 70 and the gate insulating film 30 areetched to the lower side of the low dielectric insulating film 73 togenerate an under-cut in the contact portion, and as in the method formanufacturing the semiconductor device according to the secondembodiment, in order to remove this, the photosensitive film pattern 250in the pad portion around the contact holes 74 and 78 at least is formedthinner than that in the other portions. Of course, the photosensitivefilm pattern may be formed a step-shaped so that the thickness aroundthe contact holes 72 and 74 also become thinner by forming slit patternson the mask.

[0120] Next, as shown in FIGS. 21a and b, a thin photosensitive filmformed around the contact holes 74 and 78 is removed by performing anashing process to remove some thickness of the photosensitive film, andthereafter, a low dielectric insulating film 73, which is exposed usingthe photosensitive pattern 250 as an etching mask, is etched. Then, asshown in FIGS. 21a and b, the passivation film 70 is exposed in the padportion. In the ashing process, part of the photosensitive film over thecontact holes 72 and 76 is removed to expose the borderline of the lowdielectric insulating film 73 defining the contact holes 72 and 76. Ifthe low dielectric insulating film 73 is etched using the photosensitivepattern as an etching mask, the under-cut structure is removed on thesidewalls of the contact holes 72 and 76, as shown in figures. Here, itis preferable to use a dry etching, and the etching condition having anetching selectivity between the passivation film 70 and the lowdielectric insulating film 73 should be applied. A gas mixed afluorine-substituted-gas such as SF₆+O₂, CR₄+O₂ or C₂F₆+O₂ with oxygenmay be used as an etching gas and its composition ratio is variabledepending on the forming condition of the low dielectric insulating film73.

[0121] Finally, after the photosensitive film pattern is removed, asshown in FIGS. 11 to 13, ITO or IZO having the thickness of 400 Å to 500Å is deposited, and etched using the fourth mask to form a pixelelectrode 82 connected to the conductor pattern for storage capacitorpattern 64, an assistant gate pad 84 connected the gate pad 24 and anassistant data pad 88 connected to the data pad 68.

[0122] The second embodiment of this present invention not only has theeffect according to the first embodiment but also can make themanufacturing process simplified by forming the data wire 62, 64, 65, 66and 68, the lower contact layer pattern 55, 56 and 58 thereof and thesemiconductor pattern 42 and 48 using one mask and by isolating thesource electrode 65 and the drain electrode 66 in this process. Ofcourse, also in the method for manufacturing the thin film transistorpanel for liquid crystal display according to the second embodiment, aphotosensitive film pattern is formed thin on a portion where a sealline will be formed and the low dielectric insulating film 73 in theportion is removed to expose the passivation film 70.

[0123] In the thin film transistor panel for liquid crystal displaymanufactured through such manufacturing process, as described above, apad portion and a driving integrated circuit may be electricallyconnected by a TCP or COF manner which the driving integrated circuit ispacked on a film, or by a COG manner which a driving integrated circuitis directly mounted on a substrate.

[0124] As above, according to the present invention, by forming thephotosensitive film around the contact holes thinner than the otherportions on under-cutting the lower film in the contact portion, then,performing an ashing to expose the border of the lower insulating filmin the contact portion, and hence forming the sidewall of the contacthole as a step-shaped, the under-cut can be removed in the contactportion. Through this, the display feature can be improved by preventinga disconnection generated in the contact portion to secure reliabilitythereof, and the manufacturing process cab be simplified and themanufacturing cost can be reduced by minimizing the photo etchingprocess to manufacture the thin film transistor for liquid crystaldisplay. Furthermore, the poor contact between two panels for liquidcrystal display can be improved by removing the organic film in theportion where the seal line will be formed.

What is claimed is:
 1. A method for manufacturing a semiconductor devicecomprising: forming first wire on a substrate; forming a lower film onthe first wire; forming a photosensitive pattern on the lower film usinga photosensitive material; forming contact holes for exposing the firstwire by etching the lower film using the photosensitive film as anetching mask; removing part of the photosensitive film pattern by anashing process to expose a borderline of the lower film defining thecontact holes; and forming second wire connected to the first wire viathe contact holes.
 2. The method of claim 1, wherein the lower film isformed of an insulating film made of SiNx or SiOx.
 3. The method ofclaim 1, wherein the lower film is formed of a conducting film.
 4. Themethod of claim 1, further comprising: forming the lower film of a firstinsulating film and a second insulating film; exposing the borderline ofthe lower film; and thereafter, etching the second insulating film notblocked by the photosensitive film pattern to expose the borderline ofthe first insulating film in the contact holes.
 5. The method of claim1, wherein the photosensitive film pattern around the contact holes isformed thinner than that in the otherportions.
 6. A semiconductor devicecomprising: a substrate; first wire formed on the substrate; a lowerinsulating film covering the first wire and having first contact holesfor exposing the first wire; an upper insulating film formed on thelower insulating film and having second contact holes for exposingborderline of the first contact holes; and second wire formed on theupper insulating film and connected to the first wire via the firstcontact holes and the second contact holes.
 7. The device of claim 6,wherein the upper insulating film is formed of an organic insulatingfilm or a low dielectric insulating film which has a low dielectricconstant less than 4.0 and is formed by a chemical vapor deposition. 8.A method for manufacturing a thin film transistor array panel for liquidcrystal display comprising: forming gate wire including a gate line, agate electrode connected to the gate line, and a gate pad connected toone end of the gate line; depositing a gate insulating film; forming asemiconductor layer; forming data wire including a data line crossingwith the gate line, a source electrode connected to the data electrodeand adjacent to the gate electrode, a drain electrode placed opposite tothe source electrode in relation to the gate electrode, and a data padconnected to one end of the data line; depositing an insulating film;forming a photosensitive organic insulating film pattern on theinsulating film; etching the insulating film using the organicinsulating film pattern as an etching mask to expose first contact holesfor exposing the gate pad or the data pad; performing an ashing processto expose borderline of the insulating film in the contact holes; andforming an assistant pad connected to the gate pad or the data pad viathe first contact holes.
 9. The method of claim 8, wherein the organicinsulating film pattern around the contact holes is formed thinner thanthat in the other portions.
 10. The method of claim 9, furthercomprising: forming the insulating film of a first insulating film and asecond insulating film; exposing the borderline of the insulating film;thereafter, etching the second insulating film not blocked by theorganic insulating pattern; and removing the organic insulating pattern.11. The method of claim 10, wherein the second insulating film is a lowdielectric insulating film which has a low dielectric constant less than4.0 and is formed by a chemical vapor deposition.
 12. The method ofclaim 8, wherein the organic insulating film pattern has second contactholes for exposing the drain electrode with the insulating film, furthercomprising forming a pixel electrode electrically connected to the drainelectrode via the second contact holes on the same layer as theassistant pad.
 13. The method of claim 12, wherein the second contactholes are formed with the first contact holes, and the organicinsulating pattern around the contact holes is formed thinner than thatin the other portions.
 14. The method of claim 8, wherein the thin filmtransistor array panel for liquid crystal display has a portion where aseal line for sealing a liquid crystal material is formed, furthercomprising: forming the organic insulating film pattern at the portionthinner than that at the other portions; and removing the organicinsulating film pattern at the portion by the ashing process.
 15. Themethod of claim 8, wherein both the data wire and the semiconductorlayer are formed by a photo etching process using photosensitivepatterns whose thickness is partly different.
 16. A thin film transistorarray panel for liquid crystal display comprising: gate wire formed on asubstrate, and including a gate line, a gate electrode connected to thegate line and a gate pad connected to one end of the gate line; a gateinsulating film covering the gate wire; a semiconductor layer formed onthe gate insulating layer; data wire formed on the gate insulating filmor on the semiconductor layer, and including a data line, a sourceelectrode connected to the data line and adjacent to the gate electrode,a drain electrode placed opposite to the source electrode in relation tothe gate electrode and a data pad connected to one end of the data line;an interlayer insulating film covering the semiconductor layer and firstcontact holes for exposing the gate pad or the data pad; and anassistant pad formed on the interlayer insulating film and connected tothe gate pad or the data pad via the first contact holes, wherein, theinterlayer insulating film is made of a lower insulating film and anupper insulating film formed on the lower insulating film, and, in thefirst contact holes, the borderline of the lower insulating film isformed within the borderline of the upper insulating film to expose thelower insulating film.
 17. The array panel of claim 16, wherein theupper insulating film is made of an organic insulating film or a lowdielectric insulating film having a low dielectric constant less than4.0 and formed by a chemical vapor deposition.
 18. The array panel ofclaim 16, wherein the interlayer insulating film has second contactholes for exposing the drain electrode, further comprising a pixelelectrode electrically connected to the drain electrode via the secondcontact holes in the same layer as the assistant pad.
 19. The arraypanel of claim 16, wherein, in the second contact holes, the borderlineof the lower insulating film is formed within the borderline of theupper insulating film to expose the lower insulating film.
 20. The arraypanel of claim 16, wherein the thin film transistor array panel forliquid crystal display has a portion where a seal line for sealing aliquid crystal material is formed, and the upper insulating film isremoved from the portion.